Fully synchronous pipelined RAM

ABSTRACT

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

FIELD OF THE INVENTION

[0001] This invention relates to memory circuits and, more particularly,to fully synchronous pipelined random access memory circuits.

BACKGROUND

[0002] Many high performance systems require a memory that operates witha fast system clock. Some designers use synchronous random accessmemories (“RAMs”) to meet this system requirement. For example, somesynchronous static RAMs (SRAMs) are available which use registers orlatches to temporarily store the address and control. These SRAMs use a“pipeline” scheme whereby the address to be accessed is provided duringone cycle and, during the next sequential cycle, the data is provided onthe data bus. For example, during a read operation, the address fromwhich data is to be read is provided on the nth cycle and the data readfrom the SRAM is provided on the data bus on the (n+1)th cycle. Forwrite operations, there are SRAMs that provide the address, control anddata during the same cycle and there are designs where address andcontrol are provided on the nth cycle and data is provided on the(n+1)th cycle.

[0003] The speed of the SRAM is increased because the set-up and holdtime for a register or latch is typically much shorter than the time toaccess the main array of the SRAM (the difference typically beingseveral nanoseconds). The result is to break the operations into shortercycles. On the (n+1)th cycle, the register or latch provides the storedaddress to the SRAMs main array along with the data to be written to thestored address, meeting the set-up and hold times for writing to theSRAMs main array. Because of the reduced set-up and hold time for theaddress and data on the (n+1)th cycle, the SRAMs cycle time as viewed atthe pins of the device can be significantly reduced. As a result, thefrequency of the system clock can be increased.

[0004] One problem with conventional SRAMs is that, typically, trying tointermix reads and writes in a high speed system causes a cycle to be“lost” when a memory write is immediately followed by a memory read(i.e., bus turnaround). Generally, a cycle is lost on turnaround becausethe structure of these RAMs requires an extra cycle to make sure thatall of the data is written into the memory before a read operation canbe performed. For example, if a write operation is followed by a readoperation from the same address, a lost cycle is needed so that the“new” data will be written to the specified address before the readoperation is performed on the data stored at the same address. Insystems where bus turnaround occurs frequently, the lost cycles on busturnaround can significantly reduce the bandwidth of the system. Withconventional synchronous SRAMs, the same problem can exist.

SUMMARY

[0005] According to the present invention, a fully synchronous pipelinedRAM with no lost cycles on bus turnaround is provided (i.e., the RAM iscapable of performing a read operation during any clock cycle or a writeoperation during any clock cycle without limitation).

[0006] One embodiment of the present invention, an SRAM, includes amemory, an input circuit and a logic circuit. The input circuit iscoupled to receive a memory address and control signals during any cyclereferred to as the nth cycle. During a write operation on the nth cycle,the corresponding write data to be written into the SRAM is providedduring the next, (n+1)th, cycle. During the nth cycle, the logic circuitcauses the previously stored write data to be written from the inputcircuit into the memory. The new write data associated with the addressand control signal received on the nth cycle is received into the inputcircuit on the (n+1)th cycle. The write data and the address remain inthe input circuit during any intervening read operations.

[0007] In this embodiment, when performing a read operation, the logiccircuit compares the address of the read operation to the address of themost recent write operation. If the addresses match, then the SRAMoutputs the data stored in the input circuit; however, if the addressesdo not match, the SRAM outputs the data stored in the memorycorresponding to the requested read address.

[0008] In another embodiment of the present invention, an SRAM includesan input circuit, an output circuit, a logic circuit and a memory. Inthis embodiment, the input circuit is coupled to receive a memoryaddress and control signals during any cycle referred to as the nthcycle. The output circuit includes a register to store data read fromthe memory which is read during the (n+1)th cycle. Data will then beprovided out of the output circuit on the next, (n+2)th, cycle.

[0009] The logic circuit causes the write data to be stored in a firstdata register in the input circuit two clock cycles after receipt of thewrite address and control signals. This data will move through thetwo-stage pipeline in the input circuit during intervening readoperations. Thus, write data is written into the memory during thesecond write operation after the data has been received in the inputcircuit. These operations and their associated variations will be morefully understood in accordance with the detailed description taken withthe drawings.

[0010] When performing a read operation, the logic circuit compares theaddress of the read operation to the addresses of the previous two writeoperations. If the read address matches one of the write-addressesstored in the input circuit, then the SRAM outputs to the output circuitthe data corresponding to the matched address from the input circuit tothe output circuit; if the read address matches both of thewrite-addresses stored in the input circuit, then the SRAM outputs tothe output circuit the data corresponding to the most recently writtenmatched address from the input circuit to the output circuit; however,if the addresses do not match, the SRAM outputs to the output circuitthe data stored in the memory corresponding to the requested readaddress.

[0011] This invention will be more fully understood in accordance withthe following detailed description taken with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 shows a block diagram of one embodiment of the presentinvention using a single stage pipeline.

[0013]FIG. 2 shows a more detailed diagram of the embodiment of FIG. 1.

[0014]FIG. 3 shows a timing diagram illustrating the operation of theembodiment of FIG. 2.

[0015]FIG. 4 shows a block diagram of another embodiment of the presentinvention using a two-stage pipeline.

[0016]FIGS. 5A, 5B and 5C show timing diagrams illustrating theoperation of the embodiment of FIG. 4.

[0017]FIGS. 6A and 6B illustrate the logic states of certain componentsand terminals shown in FIG. 7 for two different read/write sequencesapplied to the structure shown in FIG. 7 in the double pipelined (i.e.,two-stage pipeline) mode.

[0018]FIG. 7 shows a schematic block diagram of an embodiment of thepresent invention capable of operating in either a single pipeline ortwo-stage pipeline configuration.

[0019]FIGS. 7A and 7B show the embodiment of FIG. 7 modified for singlestage pipeline and two-stage pipeline operation, respectively.

[0020]FIGS. 8A and 8B show timing waveforms for two sequences ofread/write signals applied to the structure of FIG. 7 operating in thesingle pipeline mode and dual pipeline mode, respectively.

[0021]FIG. 9 shows an embodiment of this invention suitable forimplementation in an integrated circuit chip.

[0022]FIGS. 10A and 10B show timing waveforms illustrating the operationof the embodiment of FIG. 9 in the two-stage pipeline mode for twodifferent sequences of read/write signals.

[0023]FIG. 10C shows timing waveforms illustrating the operation of theembodiment of FIG. 9 in the one stage pipeline mode for one sequence ofread/write signals.

DETAILED DESCRIPTION

[0024]FIG. 1 shows a simplified block diagram of a single pipeline SRAM100 according to one embodiment of the present invention. Although thisembodiment utilizes SRAM memory cells, this invention also can beembodied using DRAM memory cells. SRAM 100 includes a memory 110connected to control logic 120, which is connected to an input circuit130. Input circuit 130 is coupled to receive address, control, and clocksignals from a processor or controller (not shown) on input address bus131, input control lead or bus 132, and input clock lead 134,respectively. Input data bus 133 is connected to control logic 120.

[0025] A read operation is performed as follows. During the nth cycle,the processor or controller (not shown) provides to SRAM 100 an addressto be read on bus 131. The processor or controller also indicates a readoperation by asserting (i.e. taking high) the read/write signaltransmitted on control lead or bus 132. During the (n+1)th cycle,control logic 120 compares the address of the read operation stored ininput circuit 130 to the address stored in control logic 120 during themost recent write operation. If the addresses match, then control logic120 outputs the data stored in the control logic 120 corresponding tothe most recent write operation via an output buffer 140; however, ifthe addresses do not match, control logic 120 outputs, via output portDO and buffer 140, the data stored in SRAM memory 110 corresponding tothe address of the read operation. Because the data is read from controllogic 120 when a read operation sequentially follows a write operationand the address of the data to be read corresponds to the address towhich the last received write data is to be written, no extra cycle isneeded to write the data into memory 110 before it can be read as inconventional synchronous SRAMs. As a result, lost cycles are eliminatedduring bus turnaround, thereby increasing the bandwidth of a systemusing SRAM 100.

[0026] A write operation is performed as follows. The processor orcontroller (not shown) provides to SRAM 100 an address on bus 131 duringan nth cycle. The processor or controller also indicates a writeoperation by deasserting (i.e. taking low) a read/write signaltransmitted on input control lead or bus 132. Control lead 132 may bereplaced by a bus which can then carry other control signals, such as achip enable signal and a chip select signal. The processor provides onthe (n+1)th cycle the corresponding data on bus 133 (called “writedata”) to be written to SRAM 110 during the (n+2)th write cycle at theaddress on bus 131 during the nth cycle.

[0027] Input circuit 130 receives and stores the address and control onone cycle and the corresponding write data on the next following cycle.Input circuit 130 receives the address and control and input logic 120receives the write data with a much shorter set up and hold timerelative to a typical SRAM memory, thereby allowing SRAM 100 to have ashorter cycle time.

[0028] During the (n+1)th cycle, control logic circuit 120 causes thewrite data stored in control logic 120 during the previous writeoperation to be written into SRAM memory 110 and stored there at theaddress also stored in control logic 120 associated with that writedata.

[0029] Logic circuit 120 simply holds the write data and write addressduring any intervening read operations.

[0030]FIG. 2 shows an embodiment of the SRAM system 100 in FIG. 1. Likereference numerals are used between drawings for like structures. SRAMsystem 100 includes registers A1, A3, R1 and D3. Register A3 andregister D3 each includes an enable input lead 200-1 and 200-2respectively. When register A3 or register D3 receives a logic lowsignal on enable input lead 200-1 or enable input lead 200-2,respectively, register A3 or register D3 will operate as a conventionalregister. However, register A3 and register D3 each will not alter thestored information on its output bus 205 or 221, respectively, while alogic high signal is received on enable input lead 200-1 or enable inputlead 200-2, respectively.

[0031] Registers A1, R1 and D3 are respectively coupled to receive theaddress signals via bus 131, the read/write control signal via bus 132and the data signals from the Data I/O input port via bus 133. Theoutput bus 201 of register A1 is connected to the input bus 202 ofregister A3 and to the H input port 203 of a multiplexer 204. The outputbus 205 of register A3 is connected to the L input port 206 ofmultiplexer 204. The output port 207 of multiplexer 204 is connected tothe address port of memory 110. Thus, multiplexer 204 operates toprovide either the address stored in register A1 or the address storedin register A3 to memory 110 to identify in memory 110 either theaddress from which read data is to be read or the address to which writedata is to be written.

[0032] Multiplexer 204 is controlled by the read/write signal stored inregister R1, which signal register R1 provides to the select input leadof multiplexer 204 via line 208. The stored read/write signal, whenasserted (i.e. high) to indicate a read operation, causes multiplexer204 to pass the output signals of register A1 to the address port ofmemory 110.

[0033] Conversely, the stored read/write signal, when deasserted (i.e.low) to mean a data-write operation, causes multiplexer 204 to pass theoutput signals of register A3 to the address port of memory 110; thewrite data signals in register D3 are already applied to the Data-Inport of memory 110.

[0034] In addition, the stored read/write signal, when deasserted toindicate a write operation, enables register A3 to store the outputaddress signals from register A1 and further enables new write data tobe stored in register D3, this new write data being associated with theaddress signals being transferred from address register A1 to addressregister A3. All register storage is on the rising clock edge where theclock signal transitions from low-to-high.

[0035]FIG. 3 shows a timing diagram exemplifying a series of read andwrite operations. With reference to FIGS. 2 and 3, a read operation isperformed as follows. In the nth cycle, the read/write signal intoregister R1 is asserted (i.e. goes high) on lead 132. Register R1receives and stores the asserted read/write signal on the rising edge ofthe clock signal at the end of the nth cycle (i.e. the start of the(n+1)th cycle) and outputs the asserted read/write signal at thebeginning of the (n+1)th cycle. At the same nth cycle as the read/writesignal into register R1 is asserted, register A1 receives the readaddress on input bus 131, and on the next rising edge of the clocksignal at the start of the (n+1)th cycle, stores in, and outputs fromregister A1 the address a₁ to be accessed. At the same time, address a₀stored in register A1 is transferred to register A3 since the diagramshows a write cycle at the beginning of the nth cycle. The asserted(i.e. high) read/write signal output from register R1 at the beginningof the (n+1)th cycle causes multiplexer 204 to pass address a₁ inregister A1 to memory 110. No write data is associated with the readoperation.

[0036] Assuming that the read/write signal applied on the input lead 132to control register R1 during the (n−1)th cycle represented a writeoperation, then the address a₀ stored in address register A1 during thenth cycle represents the address in memory 110 to which data d₀ is to bewritten. Data d₀, data to be written into SRAM 110 at address a₀, isapplied at the Data I/O port during the nth cycle and is stored in dataregister D3 on the low-to-high transition of the clock signal at the endof the nth cycle.

[0037] SRAM system 100 also includes a comparator 211 having an inputbus 212 connected to output port 201 of register A1 and another inputbus 213 connected to output port 205 of register A3. Consequently,during the first part of the (n+1)th cycle comparator 211 compares therequested read address a₁ (the address stored in register A1) to theaddress a₀ of the location in memory to which data d₀ in register D3will be sent on the next write clock cycle (this location is at theaddress a₀ stored in register A3). When comparator 211 detects thataddresses a₁ and a₀ match, then the read operation is reading from theaddress a₀ (stored in register A3) to which data d₀ in register D3 is tobe written in the next write operation. The updated data d₀ stored inregister D3 and corresponding to address a₀ in register A3 has not yetbeen written into memory 110; rather, the updated data d₀ is passed tothe input port 218 of mux 217.

[0038] The output lead 215 of comparator 211 is connected to select lead216 of multiplexer 217. Multiplexer 217 has an H input port 218connected by bus 221 to the output port 219 of register D3. Multiplexer217 has an L input port 220 connected to the Data-Out port of memory110.

[0039] During the read operation in the (n+1)th cycle, if comparator 211detects that address a₁ in register A1 does not match address a₀ inregister A3, then multiplexer 217 selects the Data-Out port of memory110 (i.e., data d₁ stored in memory 110 corresponding to address a₁) andoutputs this data on bus 220 through mux 217 and through buffer 140 tothe Data I/O bus. However, if comparator 211 detects that address a₁does match address a₀ in register A3, then during the (n+1)th cycle,multiplexer 217 passes the output signals d₀ on buses 221 and 218 fromthe data out port 219 of register D3 to the Data I/O bus through buffer140.

[0040] Referring to FIGS. 2 and 3, a write operation is performed asfollows. In this example, the read/write signal (i.e. R/W*) isdeasserted (i.e. taken low) during the (n+1)th cycle to indicate a writeoperation is to take place in the (n+2)th cycle. On the next transitionof the clock signal from low-to-high at the end of the (n+1)th cycle andthe beginning of the (n+2)th cycle, register R1 receives, stores andoutputs the deasserted read/write signal. Consequently, a low signal onthe select input line 208 of multiplexer 204 causes mux 204 to pass onbus 207 to the address port of SRAM 110 the output signals on bus 205representing the address a₀ stored in register A3 (which is the addressin SRAM memory 110 to which the data d₀ stored in register D3 as aresult of the previous write operation during the nth cycle is to bewritten).

[0041] Write enable circuit 210 controls the actual writing of data intoSRAM 110. Circuit 210 is enabled by the deasserted (i.e. low) writesignal as is register D3, thereby causing memory 110 to receive at theData-In port, the data signals d₀ on buses 221 and 218 from register D3on the next low clock signal (SRAM 110 is enabled by write enablecircuit 210 to write data d₀ on the low clock signal during cycle(n+2)). During cycle (n+2) the data d₀ in register D3 will be writteninto the location in memory 110 defined by the address a₀ in registerA3. Also, during cycle (n+2), register A1 receives, stores and outputsthe address a₂ to which to-be-received data d₂ applied to the Data I/Oterminal during the (n+2)th cycle is to be written in SRAM 110 on thenext write cycle.

[0042] Pulse circuit 210 provides a delayed self timed high-low-highpulse after a low-to-high clock signal after waiting the required timeto receive the stored deasserted read/write signal from register R1 viaa line 200. This pulse causes memory 110 to store at the address a₀(received from register A3 via multiplexer 204) the data d₀ received atthe Data-In port of memory 110. The Data-In port of memory 110 isconnected by buses 218 and 221 to the output port 219 of register D3,which outputs data d₀ (the data from the previous write operationassociated with address a₀).

[0043] In addition, during the (n+2)th cycle, data d₂ is applied to theData I/O terminal and thus to the input port of register D3. Data d₂corresponds to address a₂ loaded in register A1 during the low-to-hightransition of the clock signal signifying the end of the (n+1)th cycleand the beginning of the (n+2)th cycle. During the (n+2)th cycle, theread/write signal is asserted (i.e. goes high) to indicate that a readoperation associated with address a₃ will take place during cycle (n+3).

[0044] At the end of cycle (n+2), on the low-to-high transition of theclock signal, register D3 stores data is d₂ associated with address a₂.Address a₂ in register A1 is transferred to register A3 also at the endof cycle (n+2).

[0045] In the same manner as described above, the read/write signalasserted during the end of cycle (n+2)is stored in register R1 on thelow-to-high transition of the clock signal at the start of cycle (n+3).Register R1 provides the asserted read/write signal on output lead 200to disable pulse circuit 210, on output lead 200-2 to disable dataregister D3 and on output lead 200-1 to disable address register A3.Thus, on the low-to-high transition of the clock signal at the start ofthe (n+4)th cycle, address a₂ remains in address register A3.

[0046] Then, during the cycle (n+3), the read/write signal is deasserted(i.e. goes low), thereby indicating the start of another write operationduring upcoming cycle (n+4). Thus, during cycle (n+4) the output signalfrom register R1 is low thus enabling pulse circuit 210. Pulse circuit210 provides a pulse to write data d₂ from register D3 into the locationin memory 110 at address a₂ in address register A3 during cycle (n+4) adelayed time after the low-high transition of the clock signal.

[0047] Referring back to cycle (n+2), during this cycle the read/writesignal is asserted, thereby indicating a read operation. This readoperation sequentially follows a write operation (i.e., bus turnaround),which would result in a lost cycle in conventional synchronous SRAMsbecause the conventional synchronous SRAM must write the data into themain memory before this data can be read during the read operation.However, in memory circuit 100, the operation of comparator 211 andmultiplexer 217 provides the data requested by the read operation(specified by an address a₃ in register A1) if this data is d₂ (theaddress a₂ to which this data d₂ is to be written is stored in registerA3 at the start of cycle (n+3)) without first writing this data d₂ intomemory 110, thereby eliminating the lost cycle. Accordingly, an SRAMmemory system 100 will have higher system bandwidth relative to theconventional synchronous SRAM system because there is no lost cycle onbus turnaround.

[0048]FIG. 4 shows a block diagram of another embodiment of the presentinvention. In the embodiment of FIG. 4 each of the elements disclosedtherein is identical to the elements disclosed in FIG. 1 with theexception that buffer 140 has been replaced by register 440. Register440 allows the fully synchronous SRAM of this invention to be used inthe system with two pipeline delays as opposed to the single pipelinedelay system shown in FIG. 1. Thus, an output signal from SRAM 110 ispassed through control logic 120 on bus 443 to register 440 and therestored to be read out of register 440 on bus 444 in response to aclocking signal brought to register 440 on leads 441 and 442 from anexternal clock (not shown) on the next following clock cycle. Theremainder of the structure shown in FIG. 4 at the level of abstractiondepicted is identical to that shown in FIG. 1 and operates inessentially the same manner as described above in conjunction with FIGS.1, 2 and 3 but with two cycle delays associated with data to be writteninto SRAM 110 and with additional registers and logic required toimplement the two-stage pipeline delay.

[0049]FIGS. 5A, 5B, and 5C, respectively, illustrate the double pipelineread sequence for reading information from the memory of FIG. 7, thedouble pipe write sequence for writing information into the memory at aspecified address, and an illustrative double pipe read and writesequence as applied over a period of clock cycles illustrated as 0-8(FIG. 5C).

[0050] As shown in FIG. 5A, the double pipe read requires the presenceon the input bus to the first address register of an address containinginformation to be read on the first cycle, the read out from the SRAM ofthe information at the specified address in the SRAM in the second cycleand then, on the third clock cycle, the storage of this data in a systemregister and the reading out from the system register of this data.

[0051] The double pipe write shown in FIG. 5B requires the presence onthe input bus to an address register of an address of the location inmemory to which data is to be written on the first cycle, a delay forthe second cycle during which time the address on the input bus istransferred into the address register. This is followed by a third cycleduring which write data to be written into the memory is applied to theinput bus of a first data register. This data is written into the firstdata register in the system on the fourth cycle.

[0052]FIG. 7 illustrates a fully synchronous SRAM system utilizing theprinciples of this invention. As a feature of this circuit, read andwrite cycles can be intermixed without bus turnaround cycles for a readcycle following a write cycle. Edge triggered registers (i.e. registerswhich load signals previously applied to their input buses on alow-to-high clock signal transition) are used to store address, data andcontrol signals. The unique bus turnaround capability of this inventionis achieved using internal edge-triggered flip flops and various gatingand controlling logic.

[0053] In the single pipeline delay mode, read data to be output fromthe system is available at the Data I/O bus on the next clock cycleafter the read address and control signals are presented to the inputleads. A separate asynchronous output structure is available to solvehigh speed timing problems on read cycles should such problems arise.

[0054] Data for write cycles is presented to the Data I/O bus on thecycle following the cycle in which the address and control signals arepresented to the address input bus and the control signal input bus,respectively. Thus, whether read or write, the data signals are alwaysone cycle delayed from address and control signals. But the address andcontrol signals are applied to the memory simultaneously in propertiming to ensure that the data is written to or read from the propercells in the memory.

[0055] The structure shown in FIG. 7 is particularly useful in very highspeed digital applications. For example, digital signal processingmemories for recursive or nonrecursive filters or digital integratorscan move data on every clock cycle. ATM switches can have access to datacells continuously without dead cycles. High speed cache memory systemscan implement read cycles or write cycles on every clock cycle withoutinterruption caused by the memory component. In many high speedapplications, this can result in a speed improvement of up to fiftypercent (50%), for example.

[0056] In the circuit block diagram schematic shown in FIG. 7, thefollowing abbreviations are used. NAME PINS FUNCTION Address 17 Addressinputs. Word or more select in the SRAM. Data 8 Data inputs/outputs. CLK1 Clock input. All operations (except write to SRAM 710) execute on thelow-to-high transitions. R/W* 1 Read/Write input. CS* 1 Chip selectinput. When active (low), the chip is enabled. When high, the chip isdeselected and all functions are disabled. CEN* 1 Clock enable input.CpEN 1 When active (low), the chip is enabled. When not active (high),all register operations are disabled. Data still appears on the outputdata bus if the last valid operation was a read and data still appearson the input bus to be written into memory if the last valid operationwas a write. OE* 1 Output enable input. An asynchronous signal. Whenlow, the output buses are enabled. When high, the output buses are highimpedance. Sgl/Dbl* 1 When high, the data in or out is delayed by oneclock cycle. When low, the data in or out is delayed by two clockcycles. Cnt/Load* 1 When low, the address register will load the addresspresented on the address pins. When high, the address register will loadthe value currently held in the register as modified by the +1 logic;linear or other mapping. Vdd 6 Plus voltage inputs. Vss 7 Ground inputs.

[0057] With the above definitions of terms, the schematic block diagramshown in FIG. 7 will now be described. The SRAM system of FIG. 7 has theunique property of being able to read or write on every cycle with nodead cycles. The data, read or write, is always delayed by one or twoclock cycles (a function of whether a single clock cycle delay or a twoclock cycle delay is used) compared to the address and control signals.

[0058] The circuit of FIG. 7 is capable of operating either as a singlepipeline structure (one clock cycle delay) or a double pipelinestructure (two clock cycle delay). Thus, when the signal SGL/DBL*(denoted as S/D* in FIG. 7) is high, the data in/out is delayed by oneclock cycle. When SGL/DBL* is low, the data in/out is delayed by twoclock cycles.

[0059] In the schematic block diagram of FIG. 7, comparators have beengiven the numbers 701-i, where i represents a particular comparator,multiplexers have been given the numbers 703-i, where i represents aparticular multiplexer, address registers have been given the numbers704-i where i represents a particular address register, read/write(R/W*) control signal registers have been given the numbers 707-i wherei represents a particular control signal register, chip enable registershave been numbered 708-i, and two sets of registers whose uses will bedescribed shortly have been numbered 709-i and 710-i, where i equals 1or 2. Inverters have been numbered 705-i and logic gates, delays, anedge detector, an output buffer and other miscellaneous components havebeen given the numbers 706-i. Item 702 is a pulse generator. To avoidcluttering the drawing, leads and terminals have not been numbered.

SINGLE PIPELINE OPERATION

[0060] In the single pipeline configuration (i.e. one clock delayversion) of the structure of FIG. 7, S/D* is high. The operation of thestructure of FIG. 7 in the single pipeline mode (i.e. single clock delaymode) will be explained in light of the timing waveforms of FIG. 8A.

[0061] While time has been shown as starting at t₀ in FIG. 8A, thischoice is arbitrary. In any event, time t₀ should be understood torepresent some arbitrary time during the operation of the circuit andnot the start time of the circuit. This is shown in FIG. 8A by thenotation n, n+1, n+2, . . . n+8 placed above the arbitrary times t₀, t₁,t₂, . . . t₈, respectively to show that FIG. 8A describes the nththrough (n+8)th cycles of operation, where n is a selected integer.

Period t₀

[0062] During period t₀ the address signals a₀ and the R/W* signal aresupplied to appropriate input buses to the circuit. These signals areclocked into address register 704-1 and control register 707-1 on thelow-to-high clock transition at the end of period t₀ and the start ofperiod t₁. During period t₀ (and all subsequent time periods ofoperation of this circuit of FIG. 7) the select input signal Cnt/Load onthe select input lead to mux 703-1 is low thereby allowing the addresssignals a₀ applied to the address input bus of mux 703-1 to pass throughmux 703-1 to the D input bus of address register 704-1. Register 704-1is enabled by CpEn* low. Simultaneously OR gate 706-1, enabled by chipselect signal CS* low, allows the R/W* signal to pass through OR gate706-1 to the D input lead into register 707-1.

[0063] Mux 703-3 has the FLIP signal applied to its gate. This FLIPsignal is low because the signal S/D*, applied to one input lead ofinverter 705-4 is high (indicating one clock cycle delay). The outputsignal from inverter 705-4 is low so long as the system is operating inthe single pipeline mode. Therefore the output signal from AND gate706-7 will be low regardless of the states of the input signals W1 andR2 on the other two input leads to AND gate 706-7.

[0064] Similarly OR gate 706-5 receives input signals on three inputleads. The first input lead is connected to the output lead of mux703-8. Because mux 703-8 is controlled by the high S/D* signal, mux703-8 passes the CS1* signal through the S input lead. Since CS1* islow, OR gate 706-5 will have a low input signal on the input leadconnected to the output lead of mux 703-8.

[0065] Chip enable signal CpEn*, applied to the middle input lead of ORgate 706-5, is also low to enable the chip containing the circuit ofFIG. 7 to operate. The third input lead to OR gate 706-5 is connected tothe output lead of mux 703-6. The select input lead of mux 703-6 isdriven by the high S/D* signal for the single pipeline mode. The twoinput leads to mux 703-6 carry the R1 and R2 signals, respectively.Because the low output signal from mux 703-8 and the low CpEn* signalenable OR gate 706-5, the signal passed by mux 703-6 is transferredthrough OR gate 706-5 to the output lead of OR gate 706-5. This signal,depending on whether it is low or high enables or disables,respectively, data registers 709-1 and 709-2 and address registers 704-3and 704-4. When R1 is high, the output signal from OR gate 706-5 is highand when R1 is low the output signal from OR gate 706-5 is low. R1 islow only when a write signal is stored in control register 707-1. Thus,the output signal from OR gate 706-5 enables data storage registers709-1 and 709-2 and address registers 704-3 and 704-4 only when the R1signal is low indicating a write.

[0066] Referring to FIG. 8A as well as FIG. 7, the particular address a₀to which data d₀ will be written is stored in register 704-1 on therising edge of the clock signal between time period t₀ and time periodt₁, one clock cycle before the data d₀ associated with address a₀ isapplied to the Data I/O lead of the circuit.

[0067] During time period t₀, a write signal w⁻¹ is shown as stored inregister 707-1.

Period t₁

[0068] If the R/W* signal is a write signal (i.e. low) during time t₀,then the output lead R1 of register 707-1 will have a low level signalduring period t₁. The output signal W1 from inverter 705-1 will be highduring period t₁.

[0069] The output address signal a₀ at address register 704-1 is appliedto the H input bus of multiplexer 703-4. However the select input of mux703-4 is driven by the low R1 signal from register 707-1 and thereforethe address signal a₀ applied to the H input bus of mux 703-4 is notpassed through mux 703-4.

[0070] On the low-to-high transition of the clock signal at start ofperiod t₁, data d⁻¹ is transferred into clock register 709-1.

[0071] During period t₁, a new address a₁ is applied to the input bus toregister 704-1. Simultaneously data d₀ is applied through the Data I/Opin to the input bus to data register 709-1. Register 709-1 is enabledto receive and store data by the low write signal R1 on the Q outputlead of control register 707-1 is (corresponding to the signal w₀ inFIG. 8A) applied through the S input lead of mux 703-6 to one input leadof OR gate 706-5 to produce a low enable signal on the enable inputleads E of data registers 709-1 and 709-2 and address registers 704-3and 704-4. At the low-to-high transition of the clock signal betweenperiods t₀ and t₁, the control signal in register 707-1 during period t₀is transferred to register 707-2. The output signal on the Q output leadfrom register 707-2 is inverted in inverter 705-2 to yield output signalW2 which is high or low depending on the state of register 707-2.

[0072] The address a⁻¹ in register 704-1 during period t₀ is transferredto address registers 704-2 and 704-3 during the low-to-high transitionof the clock signal at the start of period t₁. This latter transferoccurs through the S input bus of mux 703-2, the select input signal towhich is S/D* which is high for the single pipeline mode of operation.The states of the select inputs on muxes 703-3 and 703-4 remain as theywere during period t₀.

[0073] Mux 703-3 passes the output address a⁻¹ on the Q output bus fromregister 704-3 and on the L input bus to mux 703-3 to the L input bus ofmux 703-4 (selected by signal R1 from control register 707-1 being low)and from there to the address port of memory 710. Thus, the address ofmemory 710 to which data d⁻¹ in data register 709-1 will be written isa⁻¹. Simultaneously, the low FLIP signal is applied to the select inputlead of mux 703-5, the output bus of which is connected to the Data-Inport of memory 710. Consequently mux 703-5 passes the data signal d⁻¹from data register 709-1 to the L input bus of mux 703-5. Because W1 ishigh when R1 is low and HOLD is high (HOLD is the inverted low outputsignal on the Q output lead from register 710-1, the input signal towhich is low CpEn*), AND gate 706-3 is enabled. The output signal fromAND gate 706-3 goes high in response to the delayed clock signal beingapplied to one input lead of AND gate 706-3 through delay 706-2. Thisclock signal causes write enable circuit 706-4 to produce a low pulse toenable the write input to SRAM 710. Consequently during the period t₁,the data d⁻¹ is read into and stored at the location in SRAM memory 710given by address a⁻¹ because the control signal in register 707-1 duringtime t₀ is a write signal w⁻¹.

Period t₂

[0074] On the low-to-high transition of the clock signal at the end ofperiod t₁ and the start of period t₂, address a₁ is entered intoregister 704-1 and address a₀, previously in register 704-1, istransferred to registers 704-2 (a “don't care”) and 704-3, replacing theaddress a⁻¹ formerly in these two registers. Simultaneously, writesignal w₁ is stored in control register 707-1. Data d₀ is transferredinto data register 709-1 and data d₁ which corresponds to the address a₁stored in address register 704-1, is placed on the input bus to dataregister 709-1 from Data I/O terminal. Data d⁻¹ is transferred fromregister 709-1 to register 709-2 (a “don't care”).

[0075] During period t₂ the clock signal is transmitted through delay706-2 and, since HOLD and W1 are both high, causes AND gate 706-3 tocause write enable circuit 706-4 to enable SRAM 710 to write into memorythe data d₀ stored in data register 709-1 at the address a₀ stored inaddress register 704-3. Address a₀ stored in address register 704-3 istransmitted to the address port of SRAM 710 on the L input bus of mux703-3 and the L input bus of mux 703-4.

[0076] Thus, by the end of period t₂, data d₀ has been placed in memory710 at the address a₀, and data d₁, corresponding to address a₁ placedin address register 704-1 at the start of period t₂, has been placed onthe input bus to data storage register 709-1.

Period t₃

[0077] At the start of the next time period t₃, the data d₁ istransferred into data storage register 709-1 and the data d₀ previouslyin this data register is transferred to data register 709-2 (a “don'tcare”). During period t₃, data d₁ is transferred into SRAM memory 710through the L input bus of mux 703-5 to the Data-In port of memory 710and stored in memory 710 at the address a₁ stored in register 704-3during the low-to-high transition of the clock signal at the start ofperiod t₃. Address a₁ is transmitted through the L input bus of mux703-3 and the L input bus of mux 703-4 into the address port of memory710 to control the location to which the data d₁ in data register 709-1is written.

Period t₄

[0078] On the low-to-high transition of the clock signal at the start ofperiod t₄, data d₁ is transmitted into data register 709-2 (a “don'tcare”) replacing the data d₀ previously in that register. Simultaneouslycontrol signal W3 is placed in control register 707-1 and the controlsignal W2 previously in register 707-1 is transferred to controlregister 707-2. Thus, signals R1 and R2 remain low reflecting the writecontrol signals stored in registers 707-1 and 707-2, respectively. Datad₂ is transferred into data register 709-1 replacing the data d₁simultaneously transmitted into data register 709-2. The address a₂previously in address register 704-1 is transferred into addressregisters 704-2 (a “don't care”) and 704-3. The address a₂ istransmitted through the L input bus of mux 703-3 to the L input bus ofmux 703-4 to the address port of SRAM 710. Simultaneously, data d₂ indata register 709-1 is transmitted through the low input bus of mux703-5 to the Data-In port of SRAM 710. Thus, data d₂ will be written toaddress a₂ in SRAM 710 upon the low write enable signal from enablecircuit 706-4 being applied to the write enabled port of SRAM 710 duringperiod t₄.

[0079] Address a₄ is placed on the input bus to address register 704-1and R/W* signal r₄, denoting a read operation, is placed on the inputbus to control register 707-1 during period t₄. The Q output lead ofregister 707-1 still carries a low level signal because write signal w₃is stored in register 707-1 and W1 from inverter 705-1 remains high. W2remains high because the previous low write signal w₂ is transferredinto control register 707-2 causing the output signal W2 from inverter705-2 to remain high. The R1 input signal on the S input lead to mux703-6 remains low thereby enabling data registers 709-1 and 709-2 andaddress registers 704-3 and 704-4.

Period t₅

[0080] On the low-to-high transition of the clock signal at the start ofperiod t₅, address a₄ is transferred into address register 704-1 andaddress a₃ previously in this register is transferred into addressregisters 704-2 (a “don't care”) and 704-3. Data d₃ is passed into dataregister 709-1 and write signal r₄ is transferred into control register707-1 thereby causing signal R1 to go high. Thus, the signal W1 frominverter 705-1 goes low. The write signal r₄ in control register 707-1causes mux 703-4 to select the signals on the H input bus for transferto the output bus connected to the address port of SRAM 710. Thus, theaddress a₃ stored in address register 704-3 is not transferred to theaddress port of SRAM 710. Rather, the address a₄ stored in addressregister 704-1 is transmitted through the H input bus of mux 703-4 tothe address port of SRAM 710.

[0081] Because a read control signal is now stored in control register707-1, a read operation is to be carried out during time period t₅. Ifthe address a₄ stored in address register 704-1 does not equal theaddress a₃ stored in address register 704-3, then the output signal Eq3from comparator 701-2 will be low. Thus, mux 703-13 will be activated topass the data out at the address a₄ in SRAM 710 through the L input busof mux 703-13 to the S input bus of output mux 703-12 activated by thehigh level signal S/D*. This output signal will then be transmittedthrough output buffer 706-9 to the Data I/O pin.

[0082] The signal R1 going high passes through mux 703-6 on the S inputlead and then through OR gate 706-5 to cause OR gate 706-5 to produce ahigh level output signal thereby disabling data registers 709-1 and709-2 and address registers 704-3 and 704-4. Consequently, at the startof the next time period, these registers will be disabled and willretain the contents which they held during period t₅.

[0083] Should, however, the address a₄ equal the address a₃ stored inaddress register 704-3, Eq3 will be high. High Eq3 will cause the datad₃ in data register 709-1 to be transmitted through the H input bus ofmux 703-13 and from there to the S input bus of mux 703-12 to the outputbuffer 706-9 and from there to the Data I/O port. Thus, the data storedin data register 709-1 does not have to be written into SRAM 710 whenaddress a₄ equals address a₃ but rather can be read out of the system tothe Data I/O bus.

[0084] Address signal a₅ and control signal r₅ are applied to the inputbus and lead, respectively, of address register 704-1 and controlregister 707-1.

Period t₆

[0085] On the low-to-high transition of the clock signal at the start oftime period t₆, address a₅ is loaded into address register 704-1.Address a₄ previously in this register is transferred to addressregister 704-2 (a “don't care”). Address a₃ previously in addressregister 704-3 remains in address register 704-3, because register 704-3has been disabled by a high level output signal from OR gate 706-5.

[0086] Simultaneously, read control signal r₅ is loaded into controlregister 707-1 and the previous read control signal r₄ in register 707-1is transferred to register 707-2. Thus, signal R1 is high and signal W1is low. Because OR gate 706-5 produced a high level output signal duringperiod t₅, data register 709-1 is disabled. Thus, throughout period t₆data register 709-1 retains the data d₃ previously placed in thatregister at the start of time period t₅.

[0087] Control signal r₅ indicates that a read of the data at address a₅is to be carried out on SRAM memory 710 during period t₆. Address a₅from register 704-1 is transmitted through the H input bus of mux 703-4selected by R1 being high to the address port of SRAM 710. If address a₅does not equal address a₄ in data register 704-2, then the signal Eq2from comparator 701-1 will be low. If a₅ does not equal a₃ stored indata register 704-3, the signal Eq3 will also be low. Thus, the data inSRAM 710 at address a₅ will be transmitted through the Data Out port andthrough the L input bus of mux 703-13 to the S input bus of mux 703-12and from there through output buffer 706-9 to the Data I/O bus from thesystem.

[0088] If, however, the address a₅ equals the address a₃ stored in dataregister 704-3, then the output signal Eq3 from comparator 701-2 will behigh. Eq3 high will cause the data d₃ stored in data register 709-1 tobe transmitted through the H input bus of mux 703-13 to the S input busof mux 703-12 and from there through buffer 706-9 to the Data I/O port.Buffer 706-9 is enabled during period t₆ as it was during period t₅ bythe high R1 output signal from control register 707-1.

[0089] Address a₆ and control signal w₆ are applied to the input bus andinput lead, respectively, of address register 704-1 and storage register707-1.

Period t₇

[0090] On the low-to-high transition of the clock signal at the start ofperiod t₇, address a₆ is loaded into address register 704-1. Address a₅previously in address register 704-1 is loaded into address register704-2. However address a₃ previously in address register 704-3 remainsin address register 704-3 because this register has been disabled by thehigh output signal from OR gate 706-5.

[0091] Simultaneously, write control signal w₆ is transferred intocontrol register 707-1. Read signal r₅ previously in control register707-1 is transferred to control register 707-2. Thus, the signal R1 goeslow and W1 goes high enabling AND gate 706-3.

[0092] The control signal w₆ means a write operation is now to becarried out on SRAM memory 710. However, the last write data to beplaced in data register 709-1 is data d₃. This data has yet to bewritten to SRAM 710. The address a₃ to which this data d₃ should bewritten is still stored in address register 704-3 which has beendisabled by the two high level read signals during periods t₅ and t₆.Thus, during period t₇ the address a₃ is transmitted from addressregister 704-3 through the L input bus to mux 703-3 to the L input busof mux 703-4 selected by the signal R1 being low, and thus to theaddress port of SRAM 710. Simultaneously, the signal d₃ in data register709-1 is transmitted on the L input bus of mux 703-5 to the data in portof SRAM 710. The clock signal passed through delay 706-2 and AND gate706-3 during cycle t₇, enables data d₃ to be written into SRAM 710 tothe address a₃ at the address port of SRAM 710.

Period t₈ and Subsequent Periods

[0093] The system operation during period t₈ and subsequent periods willbe as described above with the data to be written into or read frommemory always appearing on the Data I/O bus one cycle after the addressto which this data is to be written or from which it is to be read,appears on the input bus to the address register 704-1.

[0094] Thus, the system operates to eliminate the one cycle delay duringthe reading of data from the memory caused by the need to store in thememory the data to be written into the memory before the same data canbe read from the memory during a read operation immediately following awrite operation.

[0095]FIG. 7A illustrates the structure of FIG. 7 where all unnecessaryelements in the logic block diagram of FIG. 7 have been removed toimplement the single pipeline operation of the structure of FIG. 7. Theoperation of the structure of FIG. 7A is as described above inconjunction with FIG. 7.

DOUBLE PIPELINE OPERATION

[0096] The double pipeline operation is characterized by S/D* going low.Thus, the signal FLIP from AND gate 706-7 will be high or low dependingon the states of signals W1 and R2. Contrary to the single pipelineoperation described above, where the signal FLIP was always low becausethe signal S/D* was always high, FLIP will change from high to lowdepending on the states of the control signals in control registers707-1 and 707-2.

[0097] Also, as with FIG. 8A, while the time periods in FIG. 8B areshown as starting at time t₀, this choice is arbitrary and forconvenience only. Time t₀ represents some arbitrary time (characterizedas the nth cycle) during the operation of the circuit and not the starttime of the circuit. As with FIG. 8A, times t₁, t₂, . . . t₈ correspondto cycles n+1, n+2, . . . n+8 where n is an arbitrary integer.

Period t₀

[0098] Referring to FIGS. 7 and 8B, during period t₀, address a₀ isapplied to the input bus to address register 704-1. Simultaneously aread control signal r₀ is applied to the input lead of control register707-1. The signal S/D* is low. Accordingly, an input signal on the D*input bus to mux 703-2 is passed to the output bus of mux 703-2. Theoutput bus of mux 703-2 is connected to the D input bus of addressregister 704-3.

Period t₁

[0099] On the low-to-high transition of the clock signal CK at the startof period t₁, address signal a₀ is transferred into address register704-1. Simultaneously address a⁻¹, already in address register 704-1, istransferred to address register 704-2.

[0100] At the same time, the read control signal R/W*, shown in FIG. 8Bas r₀, on the input lead to control register 707-1, is transferred intocontrol register 707-1. The write control signal w⁻¹ in control register707-1 during period t₀ is transferred to control register 707-2. Thus,the R1 and R2 signals are high and low, respectively, and the W1 and W2signals are low and high, respectively. During period t₁, because thesignal W1 is low and the signal R2 is low, even through the D inputsignal to AND gate 706-7 is high, the signal FLIP is low.

[0101] The low S/D* signal causes mux 703-2 to transmit the address a⁻¹in register 704-2 on output bus Q to the D* input bus of mux 703-2 andthrough mux 703-2 to the D input bus of address register 704-3.

[0102] The control signal r₀ is stored in register 707-1. The controlsignal r₀ is high meaning that information is to be read from SRAM 710during time period t₁. To do this, the address signal a₀ in addressregister 704-1 is applied to the H input bus of mux 703-4. Mux 703-4 hasthe high level signal R1 on its select input lead and thus passesaddress a₀ to the address port of SRAM 710. The data stored at thelocation in SRAM 710 given by address a₀ is then passed to the Data Outport of SRAM 710 and to the low input bus of mux 703-7. Mux 703-7 passesthis data to the low input bus of mux 703-9 which in turn passes thisdata to the low input bus of mux 703-11. The select inputs of muxes703-7 and 703-9 both have low signals thereby activating their low inputbuses. The output signal from AND gate 706-6 is low because Eq2 is lowmeaning comparator 701-1 produces a low output signal. Thus, mux 703-11passes the data being read out of SRAM 710 to the D input-bus of outputregister 710-2. This data is then read into register 710-2 on thelow-to-high transition of the clock signal at the end of period t₁ andthe start of period t₂. Thus, during period t₂ the data being read outof SRAM 710 will be applied to the D input bus of mux 703-12 and fromthis D input bus to the output bus from mux 703-12 (S/D* is low therebyenabling this path). Because during period t₂ the signal R2 will behigh, this data will be passed during period t₂ from buffer 706-9(enabled by a high output signal from AND gate 706-8 reflecting the highlevel signal R2) to the Data I/O terminal from which this data will besent to its destination.

[0103] Address signal a₁ and read control signal r₁ are applied to theinput bus and input lead, respectively, of address register 704-1 andcontrol register 707-1.

Period t₂

[0104] At the start of period t₂, the low-to-high transition of theclock signal causes the address a₁ applied to the input bus of addressregister 704-1 to be stored in address register 704-1. Simultaneously,the address a₀ previously stored in address register 704-1 is stored inaddress register 704-2. The control signal r₁ indicating that theinformation stored at address a₁ is to be read out of SRAM 710, is readinto control register 707-1. The control signal r₀ previously inregister 707-1 is read into control register 707-2. Thus, the signals W1and W2 are both low and the signals R1 and R2 are both high. The data d₀read out from SRAM 710 during period t₁ and placed on the input bus D tooutput register 710-2 is transferred into output register 710-2 andtransferred on the Q output bus from register 710-2 to the D input busof mux 703-12. As described above under period t₁, this data d₀ is thenpassed from the D input bus of mux 703-12 through mux 703-12 enabled bythe S/D* signal being low, to and through output buffer 706-9 enabled bythe high level output signal from AND gate 706-8. The data d₀ beingoutput from the memory is passed through buffer 706-9 to the Data I/Oport and sent from there to its destination.

[0105] Simultaneously, the address a₁ in register 704-1 is passed to theH input bus of mux 703-4. Because the select input of mux 703-4 isdriven high by signal R1, this address a₁ is passed to the address portof SRAM 710. The information d₁ located in SRAM 710 at address a₁ isthen passed through the Data Out port from SRAM 710 to the L input busof mux 703-7 and through mux 703-7 to the L input bus of mux 703-9. Bothmuxes 703-7 and 703-9 have low input signals on their select inputs andthus pass this data d₁ to the L input bus of mux 703-11. This mux alsohas a low input signal on its select lead and thus passes the data d₁through mux 703-11 to the D input bus of register 710-2.

[0106] Address signal a₂ is applied to the input bus of address register704-1 while write control signal w₂ is applied to the input lead ofcontrol register 707-1.

Period t₃

[0107] At the low-to-high clock transition at the start of period t₃ theaddress a₂ which has previously been placed on the input bus to addressregister 704-1 during period t₂, is loaded into address register 704-1.Simultaneously, the control signal w₂ applied to the D input lead ofcontrol register 707-1 is loaded into control register 707-1. The signalr₁ previously in control register 707-1 is loaded into control register707-2. Thus, the signals W1 and W2 become high and low, respectively,and the signals R1 and R2 become low and high, respectively. At thelow-to-high clock transition at the start of time t₃, the data d₁ on theD input bus to register 710-2 (read out from the address location a₁during the previous period t₂) is transferred into register 710-2 andmade available through mux 703-12 and output buffer 706-9 to the DataI/O port.

[0108] Address signal a₃ and write control signal w₃ are applied to theinput bus and input lead, respectively, of address register 704-1 andcontrol register 707-1.

Period t₄

[0109] The control signal w₂ in register 707-1 during period t₃ meansthat in period t₄ data d₂ will be applied to the Data I/O bus and to theD input bus of register 709-1. This data d₂ will be written into SRAM710 at the address given by w₂ during a subsequent write period.

[0110] On the low-to-high transition of the clock signal at the start ofperiod t₄, the write control signal w₃ is placed in register 707-1 andthe address a₂ specifying the location in memory 710 at which data d₂ isto be stored is transferred from address register 704-1 to addressregister 704-2. The control signal w₂ is transferred from controlregister 707-1 to control register 707-2. During this period read signalr₄ is applied to the input terminal of control register 707-1 and theaddress signal a₄ is applied to the input bus of address register 704-1.During this period the data d₂ is applied to the Data I/O bus and to theD input bus of data register 709-1.

Period t₅

[0111] On the low-to-high transition of the clock signal at the start ofperiod t₅, the control signal r₄ is stored in control register 707-1,address a₄ is stored in address register 704-1 and data d₂ is stored indata register 709-1. Output signal R1 from register 707-1 is high.Output signal W1 from inverter 705-1 is low. Control register 707-2stores the write signal w₃. Thus, output signal W2 from inverter 705-2is high because w₃ is low. However, the output signal from mux 703-6remains low because the signal R2 is low. Data registers 709-1 and 709-2along with address registers 704-3 and 704-4 are disabled. In addition,AND gate 706-3 is disabled when signal W1 goes low thereby preventinginformation from being written into SRAM 710. Data d₃ is applied to theData I/O bus; data d₃ corresponds to address a₃ applied two cyclepreviously to the input bus of address register 704-1.

[0112] The address a₄ stored in address register 704-1 depicts thelocation in SRAM 710 at which information d₄ is to be read out from SRAM710. Because R1 is high this address is supplied directly through the Hinput bus of mux 703-4 to the address port of SRAM 710. Simultaneously,this address a₄ is compared in comparator 701-1 to the address a₃ storedin register 704-2 and also in comparator 701-2 to the address a₂ storedin address register 704-3. Should the address a₃ stored in addressregister 704-2 equal the address a₄ stored in address register 704-1,then Eq2 goes high. When Eq2 goes high, AND gate 706-6 produces a highoutput signal enabling mux 703-11. Data d₃ on the input Data I/O bus(corresponding to data d₄ to be read out of memory 710) is passedthrough mux 703-11 to the D input bus of register 710-2. If Eq3 goeshigh indicating address a₂ matches address a₄, then data d₂ stored inregister 709-1 (corresponding to data d₄ to be read out of memory 710)is transmitted to the H input bus of mux 703-9 enabled by Eq3 beinghigh, and through mux 703-9 to the low input bus of mux 703-11 (enabledby Eq2 low causing the output signal of AND gate 706-6 to be low) and tothe D input bus of register 710-2.

[0113] Address signal a₅ and read control signal r₅ are applied to theinput bus and input lead, respectively, of address register 704-1 andcontrol register 707-1. Data d₃ is applied to the Data I/O bus.

Period t₆

[0114] At the end of period t₅ and the beginning of period t₆, addressa₅ on the input bus to address register 704-1 is transferred intoregister 704-1 on the low-to-high transition of the clock signal.Address a₅ is then applied to the input bus of address register 704-2.During period t₅, a read signal r₅ was applied to the input lead ofcontrol register 707-1. This read signal r₅ is then transferred intocontrol register 707-1 on the low-to-high transition of the clock signalat the beginning of period t₆. The read control signal r₄ in controlregister 707-1 is transferred to register 707-2. Thus, both signals W1and W2 go low. Data d₃ is transferred into data register 709-1 and datad₂ is transferred from register 709-1 into data register 709-2 on thelow-to-high transition of the clock signal.

[0115] Address register 704-3, however, has been enabled by the lowlevel signal from OR gate 706-5 generated by R2 being low during periodt₅. Accordingly, the address a₃ on the input bus to address register704-3 during period t₅ is transferred to address register 704-3 at thebeginning of period t₆ and the address a₂ on the input bus to addressregister 704-4 during period t₅ is transferred to address register 704-4at the beginning of period t₆.

[0116] A read operation is to take place during time period t₆. Theinformation stored in SRAM 710 at address a₅ is to be read from thesystem.

[0117] Should the address a₅ not equal the address a₃ stored in register704-3 or the address a₄ stored in register 704-2, then the address a₅,transmitted to the H input bus of mux 703-4 and from there to theaddress port of SRAM 710, will determine the address within SRAM 710 atwhich the information d₅ to be read from the memory is located. Thisinformation d₅ will then be read out of SRAM 710 through the Data Outport and through the L input bus of mux 703-7, the L input bus of mux703-9, the L input bus of mux 703-11 to the input bus of register 710-2.This data d₅ will be transferred into register 710-2 on the low-to-highclock transition at the start of period t₇. Note that the comparators701-1, 701-2 and 701-3 all produce low output signals Eq2, Eq3 and Eq4,respectively.

[0118] If, however, address a₅ in address register 704-1 equals addressa₃ in address register 704-3, then, comparator 701-2 produces a highlevel output signal Eq3. A high level signal Eq3 indicates that the datad₅ to be read out from the memory system is stored in data register709-1. This data is read out from register 709-1 through the H input busof mux 703-9, the L input bus of mux 703-11, to the D input bus ofregister 710-2 and is stored in register 710-2 on the low-to-hightransition of the clock signal at the start of period t_(7.)

[0119] If the address a₅ in register 704-1 equals the address a₄ storedin register 704-2, then the signal Eq2 goes high. However the address a₄does not correspond to data being read into the system but rathercorresponds to a read signal r₄. Accordingly no data is present instorage register 709-1 or 709-2 corresponding to the address a₄ and theaddress a₅ is transmitted directly to the address input port of SRAM 710through the H input bus of mux 703-4.

[0120] Thus, in both periods t₅ and t₆, which correspond to readoperations, the data d₃ stored in data register 709-1 during period t₆,identified by the address a₃ in address register 704-3 during period t₆and by the address a₃ in address register 704-2 during period t₅, isread directly out of data register 709-1 when the address stored inaddress register 704-1 matches the address stored in address register704-3. The data d₃ is read from the Data I/O bus when the address a₄stored in register 704-1 matches the address a₃ stored in register 704-2during period t₅.

[0121] The address signal a₆ and write control signal w₆ are applied tothe input bus and input lead, respectively, of address register 704-1and control register 707-1. Data d₄ corresponding to the information ator to be placed at address a₄ in memory 710 is placed on the Data I/O.

Period t₇

[0122] On the low-to-high transition of the clock signal CK at the startof period t₇, address a₆ located on the input bus to address register704-1 during period t₆, is transferred into and stored in addressregister 704-1. Simultaneously, the address a₅ previously stored inaddress register 704-1 is transferred to address register 704-2. Duringperiod t₆, R2 was high. Thus, data registers 709-1 and 709-2 and addressregisters 704-3 and 704-4 were disabled. These registers are alsodisabled during time period t₇. Consequently, the data d₃ in dataregister 709-1 and the data d₂ in data register 709-2 during period t₆remain in place in these registers on the low-to-high clock signaltransition at the start of period t₇. In addition, the addresses a₃ anda₂ in address registers 704-3 and 704-4, respectively, likewise remainin place. Thus, during period t₇, write signal w₆ is stored in controlregister 707-1 while read signal r₅ is stored in control register 707-2.Thus, a write operation is to take place and the data to be written intoSRAM 710 is the data d₂ associated with the address a₂ stored in addressregister 704-4. This data d₂ is stored in register 709-2. Because bothR2 and W1 are high, the FLIP signal from AND gate 706-7 is high. Thus,mux 703-5 provides the data from the Q output bus of data register 709-2through the H input bus of mux 703-5 to the Data In port of SRAM 710.Meanwhile the address a₂ stored in register 704-4 is provided throughthe H input bus of mux 703-3 to the L input bus of mux 703-4 to theaddress port of SRAM 710. The L input bus of mux 703-4 is activated bythe low level signal R1 on the select input of mux 703-4.

[0123] As shown in FIG. 8B, a write signal w₆ had been applied to theinput lead of control register 707-1 during period t₆. This write signalw₆ is now stored in control register 707-1. Thus, output signal R1 goeslow causing signal W1 to go high. R2 is still high thereby stilldisabling data registers 709-1 and 709-2 and address registers 704-3 and704-4. Because address register 704-3 had previously been disabledduring period t₆, the address a₅ on the input bus to address register704-3 is not stored in address register 704-3. Rather, address a₃previously in address register 704-3 during period t₆ remains stored inthis register. Data d₃ likewise remains stored in data register 709-1for the same reason. The signal W1 goes high on the low-to-high clocktransition at the beginning of period t₇ thereby causing AND gate 706-3to produce a high output signal which enables write circuit 706-4 tocause the writing of information into SRAM 710 when the clock signalgoes high to enable circuit 706-4 during period t₇. Thus, during periodt₇, a write signal is generated by write enable circuit 706-4 whichcauses the data d₂ stored in data register 709-2 to be transmittedthrough the H input bus of mux 703-5 to the Data In port of SRAM 710 andstored at the address a₂ applied to the address port of SRAM 710 throughthe L input bus of mux 703-4 and the H input bus of mux 703-3 from the Qoutput bus of address register 704-4.

[0124] Address signal a₇ and write control signal w₇ are applied to theinput bus and input lead, respectively, of address register 704-1 andcontrol register 707-1.

Period t₈

[0125] On the low-to-high transition of the clock signal at the start ofperiod t₈, address a₇ on the input bus of register 704-1 is stored inregister 704-1. Address a₆ in register 704-1 during period t₇ istransferred to and stored in register 704-2. Registers 704-3 and 704-4,however, are still disabled by the high level signal R2 transmittedthrough OR gate 706-5. Therefore registers 704-3 and 704-4 continue tohold the addresses a₃ and a₂, respectively. The data in data registers709-1 and 709-2 likewise remains d₃ and d₂ respectively. The signal w₇on the input lead to control register 707-1 during period t₇ istransferred into control register 707-1. Signal w₆ previously in controlregister 707-1 is transferred to control register 707-2. The signals R1and R2 become low. Consequently, the FLIP signal from AND gate 706-7changes from high to low and thereby enables the L input bus of mux703-5. Consequently, the data d₃ in data register 709-1 is transferredthrough the L input bus of mux 703-5 to the Data In port of SRAM 710.Simultaneously, the address a₃ stored in address register 704-3 istransmitted through the L input bus of mux 703-3 to the L input bus ofmux 703-4 thereby to the address port of SRAM 710. Consequently, thedata d₃ is stored in SRAM 710 at the address a₃ during period t₈.

[0126] As can be seen from the above description, in the dual pipelineversion of the invention, data to be written into the memory is appliedto the Data I/O two clock periods after the write signal associated withthat data is applied to the control circuit. Thus, a read signalimmediately following a write signal occurs before the data associatedwith that write signal even appears on the Data I/O port. The data readout from the SRAM memory during the next cycle will be stored in aregister prior to being transmitted on the second following clock cycleto the Data I/O port. Thus, the Data I/O port will at all times eitherhave input data being transmitted into the system or output data beingtransmitted from the system. The system basically allows data beingwritten into the system to be held in suspense during the reading out ofdata from the system. The reading out of data from the system causes theaddresses of the two sets of data being written into the system butstill in the double pipeline to be checked to determine if the databeing read out is one of these two pieces of data. If it is, the systemautomatically reads out the correct data from a temporary storageregister; if it is not, the system automatically reads out the correctdata from SRAM 710.

[0127]FIG. 7B illustrates the components of FIG. 7 which are required toimplement the double pipeline version of this invention. The operationof the structure in FIG. 7B is as described above in connection with thedouble pipeline operation of the structure shown in FIG. 7. The elementsin FIG. 7B are numbered identically to the corresponding elements inFIG. 7.

INTEGRATED CIRCUIT EMBODIMENT

[0128]FIG. 9 shows the structure of this invention as implemented in thepreferred embodiment incorporated in a semiconductor integrated circuitchip. The waveforms shown in FIGS. 10A and 10B illustrate the operationof the embodiment of this invention shown in FIG. 9 in the dual pipelinemode for two sequences of operations. In FIG. 10A the sequence of readread write write read read write write read read is described. In FIG.10B the sequence of read write read write read write read read isdescribed. Naturally, in operation, any sequence of read and writesignals can be applied to the circuit. The waveforms shown in FIGS. 10Aand 10B are merely illustrative of two possible sequences of such readand write signals.

[0129] Turning to FIG. 9, the signals depicted in FIG. 9 are as follows:XENB = Enable signal (Low to enable) XADDR = Address CLK = Clock S/DB =Single Pipeline (high)/Double Pipeline (low) XWEB = Write (low)/Read(high) XIO = Data signals, Input/output XCSB = Chip Select-Low to SelectEQX = Comparator-last address-AX to AR EQY = Comparator-Second to lastaddress AY to AR DX = Last data received DY = Second to last datareceived XOEB = Output buffer enable signal AX = Address in register804-2 AY = Address in register 804-3 WXB = Output signal from controlregister 807-2 Dout = Data out from memory array 810 XDin = Data In toSystem WB = output signal from register 807-1 RB = Inverted outputsignal from register 807-1

Time Period t₀

[0130] At the beginning of time t₀ (an arbitrary time during theoperation of the system picked solely for illustrative purposes), on thelow-to-high transition of the clock signal, the address a₀ istransferred into the address register 804-1. Simultaneously, the controlsignal XWEB, corresponding to a read, is transferred into controlregister 807-1. The chip select signal XCSB (not shown in FIG. 10A),which is low to select a particular chip, is applied to the D input leadof and is thus stored in register 808-1. The output signal CSB fromregister 808-1 is passed to one input lead of OR gate 805-4 and thus CSBwhen low enables this OR gate to pass the Q output signal from register807-1. CSB is also passed through inverter 812-1 which, when CSB is low,produces a high level signal CS which enables the NAND gate 805-3. Thus,the signal RB output from NAND gate 805-3 is the complement of signal WBfrom OR gate 805-4. Because at the start of time period t₀ a readcontrol signal is transferred into the system, address a₀ in memoryarray 810 is applied through the H input bus of mux 803-2 (selectedbecause WB is high to indicate a read operation is taking place) to theaddress port of memory array 810. The data in memory array 810 ataddress a₀ is then placed on the output bus OUT from memory array 810and then transmitted through a buffer 812-3 to the input bus to dataregister 811-1. This data is then stored in register 711-1 on thelow-to-high transition of the clock signal at the end of period t₀ andthe beginning of period t₁.

Time Period t₁

[0131] During period t₁ a write signal w₁ has been applied to controlregister 807-1 and the read signal r₀ previously in control register807-1 is transmitted through OR gate 805-4 to control register 807-2.Signal CSB remains low as it will during all operations. Thus, thesignal WXB represents the control signal in register 807-1 during thepreceding time period t₀ whereas the signal WB represents the controlsignal in register 807-1 during the current time period t₁. Becauseduring period t₁ a write operation is being called for, the address a₁stored in register 804-1 represents the address to which data d₁, to beapplied to the XIO pin in the next clock cycle after the address a₁ isstored in register 804-1, is to be stored in memory array 810. This datad₁ will be transmitted into data register 809-1 two cycles after theaddress a₁ is transferred into register 804-1.

[0132] The data stored in register 811-1 during time period t₁ istransmitted through the L input bus of mux 803-5, enabled by the lowlevel S/DB signal, to output buffer 812-4 and from there to the XIO busof the system. Buffer 812-4 is enabled by a high level signal from ANDgate 805-10. Gate 805-10 is enabled by the high level signal WXB storedin register 807-2 and the high level signal CSX from mux 803-3. The highlevel signal CSX reflects the high level output signal from inverter812-1 during time period t₀ stored in register 808-2 on the low-to-hightransition of the clock signal at the start of period t₁. This highlevel signal is passed through the L bus of mux 803-3 to become the CSXoutput signal from mux 803-3.

Time Period t₂

[0133] During time period t₂, a write operation is also called for.Thus, on the low-to-high transition of the clock signal at the start ofperiod t₂, write signal w₂ is transferred into control register 807-1and the write signal w₁ previously in control register 807-1 istransferred into control register 807-2. Accordingly, WB and WXB becomelow level signals. The address a₂ is stored in address register 804-1and the address a₁ previously stored in address register 804-1 istransferred to address register 804-2. Data d₁ is applied to the inputdata bus XIO and will be transferred into data register 809-1 on thelow-to-high transition of the clock signal at the start of the next timeperiod t₃.

Time Period t₃

[0134] At the low-to-high transition of the clock signal at the start oftime period t₃, the data d₁ on the input bus XIO is transmitted intodata register 809-1. Also at approximately the same time a new addressa₃ is placed in address register 804-1 and the address a₂ previously inregister 804-1 is transferred to address register 804-2. The address a₁previously in address register 804-2 is transferred to address register804-3. The read signal r₃ is transferred into control register 807-1 andthe write signal w₂ previously in control register 807-1 during periodt₂ is transferred into register 807-2.

[0135] The address signal a₃ stored in register 804-1 is transmittedthrough the H input bus of mux 803-2, selected by signal WB being high,to the address port of memory array 810. Because a read operation isbeing called for, if address a₃ stored in address register 804-1 equalsthe address a₂ stored in address register 804-2 or the address a₁ storedin address register 804-3, then comparator 801-1 will produce a highoutput signal EQX or comparator 801-2 will produce a high output signalEQY, respectively. If address a₃ equals address a₁ then the high levelsignal EQY passed through inverter 812-2 causes NAND gate 805-6 toproduce a low level signal thereby disabling buffer 812-3. Thus, nooutput signal will be transmitted from memory array 810 to the outputregister 811-1. However because EQY is high and EQX is low, and WXB islow then the output signal of AND gate 805-9 is high and the outputsignal of OR gate 805-8 is high thereby enabling buffer 812-6 to passdata d₁ (DX, the last data received) from register 809-1, to the inputbus to output register 811-1. Thus, the data d₁ stored in data register809-1 will be stored in output register 811-1 on the low-to-hightransition of the clock signal at the start of time period t₄.

[0136] If address a₃ equals address a₂ then the high level signal EQXpassed through inverter 812-5 causes NAND gate 805-6 to produce a lowlevel signal thereby disabling buffer 812-3. Thus, no output signal willbe transmitted from memory array 810 to the output register 811-1.However, because EQX is high and WXB is low reflecting the fact that awrite signal w₂ was stored in control register 807-1 during time periodt₂ and is stored in register 807-2 during time period t₃, AND gate805-12 produces a high level output signal enabling buffer 812-12 topass the data d₂ on the input bus XIO to the system corresponding toaddress a₂ in register 804-2 to output register 811-1. Thus, the data d₂is passed to the input bus of output register 811-1 to be stored in thisregister on the low-to-high transition of the clock signal at the startof period t₄.

Time Period t₄

[0137] During time period t₄, read signal r₄ is stored in controlregister 807-1 and previous read signal r₃ is stored in control register807-2. Simultaneously, on the low-to-high transition of the clock signalat the start of period t₄, address a₄ is stored in address register804-1. Data d₁ stored in data register 809-1 is transferred to dataregister 809-2 and data d₂ on the XIO input bus is transferred into dataregister 809-1. Because the signal WB passed through OR gate 805-1 ishigh at the end of time period t₃ and also at the start of time periodt₄, address registers 804-2 and 804-3 are disabled and thus retain theaddresses a₂ and a₁, respectively. The address a₄ is compared to theaddresses stored in address registers 804-2 and 804-3, respectively. Ifthe address a₄ equals the address a₂ stored in address register 804-2 orthe address a₁ stored in address register 804-3 then the signal EQX orEQY, respectively will be high. If EQY is high, then EQX will be low andthe address a₁ stored in address register 804-3 corresponds to the datad₁ stored in data register 809-2. Signal WXB is now high levelreflecting the storage of the signal r₃ in control register 807-2.Consequently, AND gate 805-11 produces a high level output signal whichenables buffer 812-10 to pass the data d₁ represented by signal DY,stored in data register 809-2, to the input bus of output register811-1. Data d₁ will be stored in output register 811-1 on thelow-to-high clock transition of the clock signal at the start of timeperiod t₅.

Time Period t₅

[0138] During time period t₅, data in register 811-1 will be passedthrough the L input bus of mux 803-5 (selected by signal S/DB being low)to output buffer 812-4 and from there to the Data I/O pin XIO to be sentoutside the system.

[0139] During time period t₅ a write signal w₅ is stored in controlregister 807-1 and the read signal r₄ previously in this controlregister is transferred to and stored in control register 807-2. Addressa₅ is stored in address register 804-1 but address registers 804-2 and804-3 continue to store addresses a₂ and a₁, respectively because thesetwo registers are still disabled by the read signal r₄ at thelow-to-high transition of the clock signal at the start of time periodt₅.

[0140] Because this is a write operation, the data d₁ in data register809-2 is to be written into memory array 810 at the address a₁ stored inaddress register 804-3. The system writes data into memory array 810 onthe second write operation after the address to which the data is to bewritten is stored in address register 804-1. Signal WB is low thereforethe mux 803-2 passes the address a₁ in address register 804-3 directlyto the L input bus of mux 803-2 to the address port of memory 810.Simultaneously, the data DY stored in data register 809-2 is appliedthrough the H input bus of mux 803-7 selected by the high signal WXBfrom control register 807-2 passed through the L input bus of mux 803-6(selected by the low S/DB signal) to the L input bus of mux 803-8 (alsoselected by the low S/DB signal) to the select input lead of mux 803-7.Thus, the data d₁, represented in FIGS. 9 and 10A by the signal DY, ispassed through the H input bus of mux 803-7 to the Data In port ofmemory array 810 and stored in memory array 810 at the location given byaddress a₁ in register 804-3.

Time Period t₆

[0141] On the low-to-high transition of the clock signal at the start oftime period t₆, address a₆ is placed in address register 804-1 andaddress a₅ previously in this register is transmitted to addressregister 804-2.

[0142] Address a₂ previously in address register 804-2 is transferred toaddress register 804-3. Control signal w₆, a write signal (low), istransferred into control register 807-1 and control signal w₅, also awrite signal (low), is transferred from control register 807-1 tocontrol register 807-2. Data d₁ remains in register 809-2 and data d₂remains in register 809-1 because these registers are disabled by thehigh level signal WXB from control register 807-2 passed to the L inputbus of mux 803-6 and from there through OR gate 805-5 (enabled by thelow XENB signal) to disable data registers 809-1 and 809-2.

[0143] A write operation is to take place during time period t₆. Thiswrite operation involves the transfer of the data d₂ in data register809-1 into SRAM 810 at the address a₂ now stored in address register804-3. Because WB is low reflecting the write signal w₆ stored incontrol register 807-1, the address a₂ is transmitted from addressregister 804-3 through the L input bus of mux 803-2 to the address portof memory array 810.

[0144] Data d₂, however, is stored in data register 809-1. The data d₂in data register 809-1 is transmitted through the L input bus of mux803-7 selected by the low output signal from mux 803-8 transmitted fromthe WXB output lead of control register 807-2 through the L input bus ofmux 803-6 to the L input bus of mux 803-8 to the select input lead ofmux 803-7. The low signal WXB (note that WXB goes low during period t₆because write signal w₅ is transmitted into register 807-2 during periodt₆) thus ensures that the data d₂ is passed through mux 803-7 from dataregister 809-1 to the Data In port of memory array 810 and placed at thelocation in memory array 810 given by address a₂ during period t₆.

[0145] Data d₅, corresponding to address a₅, is placed on the input busXIO.

Time Period t₇

[0146] At the low-to-high transition of the clock signal at the start ofperiod t₇, address signal a₇ is stored in address register 804-1.Addresses a₆ and a₅ are transferred to address registers 804-2 and804-3, respectively. Read signal r₇ is transmitted into and stored inthe control register 807-1 and the write signal w₆ previously inregister 807-1 is transferred into and stored in register 807-2. Data d₅corresponding to the write address a₅ received and stored in addressregister 804-1 during period t₅, is stored in data register 809-1 andthe data d₂ previously stored in register 809-1 is transferred to andstored in register 809-2. WXB is low and thus data registers 809-1 and809-2 are enabled. Because a read operation is being carried out duringperiod t₇, the data stored in memory array 810 at address a₇ is to beread out of the memory array. However, if this data corresponds to thedata at the address a₆ stored in address register 804-2 or to the dataat the address a₅ stored in address register 804-3, EQX or EQY fromcomparator 801-1 or comparator 801-2 will be high, respectively. Underthese circumstances, the data d₅ stored in data register 809-1 or thedata d₆ applied to the Data I/O port (shown as signal XIO) will beselected to be transferred to the input bus to storage register 811-1.If the data d₆ is selected, reflecting the high level EQX signal, thenWXB, which is low, will be inverted by inverter 812-13 and applied toone input lead of AND gate 805-12. The high level signal EQX will beapplied to the other input lead of AND gate 805-12 causing AND gate805-12 to produce a high level output signal which enables buffer812-12. Buffer 812-12 transmits the data signal d₆ on the input I/O busdirectly to the input bus to register 811-1 to be stored in register811-1 on the low-to-high transition of the clock signal at the start ofthe next time period t₈. Thus, during period t₈, the data d₆ stored inregister 811-1 will be read out of register 811-1 through the L inputbus of mux 803-5 and through the output buffer 812-4 (enabled by WXB andCSX both high and XOEB low) to the I/O output bus. The circuit continuesto operate as described above as additional read and write signals areapplied to the circuit.

[0147]FIG. 10B illustrates the operation of the circuit of FIG. 9 forthe sequence of control signals read, write, read, write, read, write,read, read.

Time Period t₀

[0148] At time t₀ (t₀ is a time arbitrarily selected during theoperation of the system), the address signal a₀ is loaded into addressregister 804-1. A high level signal XWEB corresponding to a read r₀ isloaded into control register 807-1.

Time Period t₁

[0149] At the low-to-high transition of the clock signal at the start ofperiod t₁, address a₁ is loaded into address register 804-1. Because thesignal WB is still high, reflecting the read control signal r₀ incontrol 807-1 during time period t₀, OR gate 805-1 produces a highoutput signal disabling address registers 804-2 and 804-3. Therefore theaddress a₀ in register 804-1 is essentially lost and replaced withaddress a₁. The control signal w₁, a low write signal, is read intocontrol register 807-1 causing the signal WB to become low and thesignal RB output from NAND gate 805-3 to become high. The write signalw₁ indicates that data d₁ is going to be applied to XIO, the Data I/Oterminal, is sometime during the next clock period and will be writteninto the data register 809-1 during the second following clock period.Meanwhile any data d₀ being read out of the system as a result of theread control signal during period t₀ is transferred into output register811-1 on the low-to-high transition of the clock signal at the start ofthe time period t₁. This data d₀, the data at address a₀ in memory array810, is transferred through buffer 812-3 enabled by EQY and EQX bothbeing low thereby causing the output signal from AND gate 805-6 to behigh and thus enable buffer 812-3. From register 811-1, this data d₀ istransmitted on the L input bus of mux 83-5, through buffer 812-4, to theData I/O.

Time Period t₂

[0150] On the low-to-high transition of the clock signal at the start ofperiod t₂, address a₂ is read into address register 804-1. Address a₁previously in address register 804-1 is transferred into addressregister 804-2, enabled by the low write signal WB during time periodt₁. Any address in address register 804-2 is also transferred throughmux 803-1 to address register 804-3 during the same low-to-hightransition of the clock signal. The read signal r₂ is transferred intocontrol register 807-1 and the low level write signal w₁ previously incontrol register 807-1 during time period t₁ is transferred to controlregister 807-2. Therefore WXB, the output signal from control register807-2 is low during time period t₂. Because the operation during timeperiod t₂ is a read, information contained at address a₂ in SRAM memory810 is transferred to the data output of memory array 810 and throughenabled buffer 812-3 to the input port of register 811-1. If, however,the address a₂ stored in address register 804-1 of the information to beread from the memory system is equal to the address a₁ stored in addressregister 804-2, comparator 804-1 produces a high level signal EQX. Highlevel signal EQX disables buffer 812-3 and means that the data d₁ beingapplied to the input bus XIO during time period t₂ must also betransferred to the input bus of the output register 811-1 because thisis the data to be read out from the circuit during period t₂ in responseto the read signal r₁. This data d₁, represented by the signal XIO, isapplied directly to the input bus to buffer 812-12. Buffer 812-12 isenabled by the high level EQX signal from comparator 801-1 together withthe low level signal WXB inverted by inverter 812-13 to produce a highlevel output signal from NAND gate 805-12. Thus, the data d₁ on theinput bus XIO is transferred to the input bus D of output register811-1.

Time Period t₃

[0151] On the low-to-high transition of the clock signal at the start oftime period t₃, the data d₁ on the input bus D of output register 811-1is transferred into register 811-1. The data d₁ is also transferred intodata register 809-1 and the address a₃ is transferred into addressregister 804-1. Write control signal w₃ is transferred into controlregister 807-1 and the read control signal r₂ previously in controlregister 807-1 is transferred through OR gate 805-4 enabled by the lowlevel CSB signal from chip select register 808-1 to control register807-2. Thus, the signal WXB goes high. Because during time period t₂ thesignal WB is high level, the address signal a₂ in register 804-1 is nottransferred into address register 804-2 and the address signal a₁ inaddress 804-2 remains in address register 804-2. The write signal w₃ isstored in control register 807-1. Thus, the signal WB goes low. Theaddress stored in register 804-3 is transferred through the L input busof mux 803-2 to the address port of memory array 810. The datapreviously in data register 809-2 is transmitted through the H input busof mux 803-7 (selected by the high WXB signal passed through the L inputbus of mux 803-6 and the L input bus of mux 803-8) to the Data In portof memory array 810. WXB going high disables data registers 809-1 and809-2 so that on the low-to-high transition of the clock signal at thestart of the next time period t₄, the data in these two registers willremain in place and not be transferred. However, the address registers804-2 and 804-3 are enabled so that the addresses in registers 804-1 and804-2 can be transferred to registers 804-2 and 804-3, respectively, onthe low-to-high transition of the clock signal at the start of time t₄.

Time period t₄

[0152] On the low-to-high transition of the clock signal at the start oftime period t₄, address a₄ is loaded into address register 804-1.Address a₃ previously in address register 804-1 is transferred toaddress register 804-2 and address a₁ previously in address register804-2 is transferred to address register 804-3. The read signal r₄ istransferred into control register 807-1 and the write signal w₃previously in control register 807-1 is transferred through OR gate805-4 into control register 807-2. Thus, the signal WXB goes low. Theread signal r₄ means that information d₄ contained in memory array 810at the location given by address a₄ is to be read out of memory array810. If, however, the address a₄ equals the address a₃ stored in addressregister 804-2 or equals the address a₁ stored in address register804-3, the output signal EQX from comparator 801-1, or the output signalEQY from comparator 801-2, goes high. If both EQX and EQY are not high,then the data stored at address a₄ is passed through the Data Out portfrom SRAM 810 and through buffer 812-3 to the input bus of outputregister 811-1. On the low-to-high transition of the clock signal at thestart of the next time period t₅, this data will be loaded into outputregister 811-1 and passed through the L input bus of mux 803-5 to buffer812-4 and then read out of the system. If however EQX is high then theaddress a₄ of the data to be read out from the memory array equals theaddress a₃ stored in address register 804-2. The address a₃ correspondsto data d₃ placed on the input bus XIO. EQX being high and WXB being low(to reflect the write signal w₃ stored in control register 807-2) causesAND gate 805-12 to produce a high output signal to enable buffer 812-12.The data signal d₃ is thereby passed directly to the input bus of outputregister 811-1. This data signal d₃ will then be stored in outputregister 811-1 on the low-to-high transition of the clock signal at thestart of time period t₅.

[0153] Alternatively, if EQY is high, then the address a₄ equals theaddress a₁ stored in address register 804-3. The address a₁ correspondsto the data d₁ stored in data register 809-1. Accordingly, the data d₁(corresponding to the signal DX) is read out of the system throughbuffer 812-6. Buffer 812-6 is enabled by a high output signal from ANDgate 805-9 caused by a high signal EQY applied to one input lead and lowsignals EQX and WXB applied to and inverted by inverters 812-8 and812-9, respectively. Thus, the data d₁ is transferred through buffer812-6 to the input bus of output register 811-1 to be loaded into outputregister 811-1 on the low-to-high transition of the clock signal at thestart of the next time period t₅.

[0154] The system continues to operate as described above with the datacorresponding to a given write signal being written into memory array810 two write cycles following the loading of the address correspondingto that data into address register 804-1.

SINGLE PIPELINE OPERATION OF THE CIRCUIT OF FIG. 9

[0155] While the circuit in FIG. 9 has been described in conjunctionwith the dual pipeline operation, the single pipeline operation of thecircuit requires the signal S/DB to be high. Thus, muxes 803-1, 803-3,803-5, 803-6 and 803-8 will all have their high input buses selected forthe transmission of signals to the output bus from the mux. FIG. 10Cillustrates the timing waveforms associated with the system shown inFIG. 9 for the single pipeline delay.

Time Period t₀

[0156] On the low-to-high transition of the clock signal at the start oftime period t₀ (a time arbitrarily selected after the system has begunoperating), address a₀ is read into address register 804-1. Read signalr₀ is read into control register 807-1. Thus, the signal WB is high andthus the address a₀ is transmitted directly through the H input bus ofmux 803-2 to the address port of memory array 810.

[0157] The address a⁻¹ is transferred simultaneously into addressregister 804-2 and address register 804-3, the latter register receivingthe output signal from mux 803-1, the input signal to mux 803-1 beingapplied to the H input bus directly from the output bus of register804-1. If address a₀ equals address a⁻¹ stored in both registers 804-2and 804-3, then both EQX and EQY from comparators 801-1 and 801-2 arehigh. The high EQY signal causes mux 803-4 to pass the DX signalreflecting the data signal in register 809-1 through the H input bus ofmux 803-4 to the H input bus of mux 803-5 and from there through buffer812-4 to the XIO pin of the circuit. Because EQY is high, the signal DXis the data d⁻¹ stored in data register 809-1. Note that in the singlepipeline mode, signals EQX and EQY are both simultaneously high orsimultaneously low because the same address is stored in both dataregisters 804-2 and 804-3.

Time Period t₁

[0158] On the low-to-high transition of the clock signal at the start oftime period t₁, the address signal a₁ is written to address register804-1. Because the signal WB is high at the start of time period t₁, theaddress registers 804-2 and 804-3 retain their contents, namely theaddress a⁻¹ in both registers. Because a write signal w₁ is stored incontrol register 807-1 and the previous read signal r₀ is stored incontrol register 807-2, the signal WB is low and the signal RB is high.Because the write operation is to take place, and because WB is low, theaddress a⁻¹ stored in address register 804-3 is transmitted directlythrough the L input bus of mux 803-2 (selected because the controlsignal WB is low). The data d⁻¹ in data register 809-1 is then writteninto memory array 810 at the address a⁻¹ stored in address registers804-2 and 804-3.

Time Period t₂

[0159] On the low-to-high transition of the clock signal at the start oftime period t₂, the address signal a₂ is written to address register804-1. Because the signal WB is low at the start of time period t₂, theaddress a₁ in address register 804-1 is transferred to register 804-2and also to 804-3. On the low-to-high transition of the clock signal atthe start of time period t₂, the write signal w₂ is transferred intocontrol register 807-1. The previous write signal w₁ stored in controlregister 807-1 is transferred to control register 807-2. Thus the signalWXB is low as is the signal WB. The data d₁ is stored in data register809-1 and the data d⁻¹ is transferred from data register 809-1 to dataregister 809-2. Because WB is low, the address a₁ in address register804-3 is transmitted directly to the address port of SRAM 810 and thedata d₁ in data register 809-1 is transmitted directly to the Data Inport of SRAM 810 to be stored there at address a₁. The data d₂corresponding to the address a₂ is placed on the Data I/O pin during thetime period t₂.

Time Period t₃

[0160] On the low-to-high transition of the clock signal at the start oftime period t₃, the address signal a₃ is read into address register804-1. Simultaneously the data d₂ placed on the input bus XIO during thelatter portion of time period t₂ is read into data register 809-1 andthe data d₁ previously in data register 809-1 is transferred to dataregister 809-2. Both of these registers are enabled at the start of timeperiod t₃ by the low level write signal w₂ stored in control register807-1 during time period t₂. This low level signal is transferredthrough the H input bus of mux 803-6 and through one input lead of ORgate 805-5 to enable these two data registers.

[0161] On the low-to-high transition of the clock signal at the start oftime period t₃, the signal w₂ in control register 807-1 is transferredto control register 807-2 and the signal r₃, a read signal, istransferred into control register 807-1. The signal WB becomes highlevel thereby selecting the H input bus of mux 803-2 which passes theaddress a₃ from address register 804-1 through mux 803-2 to the addressport associated with memory array 810. Simultaneously the address a₂previously in address register 804-1 is stored in address registers804-2 and 804-3.

[0162] If address a₃ equals address a₂, then both EQX and EQY go highthereby both disabling buffer 812-3. EQY high selects the H input bus ofmux 803-4 which thereby passes to the H input bus of mux 803-5 andthrough the output buffer 812-4 to the XIO port the data d₂ associatedwith the address a₂.

[0163] Thus, the single pipeline delay system operates to either readout of memory the data at the address associated with a read controlsignal or to read out of a data storage register the data associatedwith the address of the location in memory to be read from when thataddress is the immediately preceding address of data to be written tothe memory.

[0164] While several embodiments of this invention have been described,other embodiments of this invention will be obvious to those skilled inthe art. In particular, embodiments involving three or more pipelinedelays will be obvious in view of this disclosure. Also, while a singleData I/O terminal is shown in FIGS. 7, 7A and 7B, for example, forreceiving data to be written into or being read from the memory 710, inpractice separate data input and data output terminals can be used, ifdesired.

I claim:
 1. A synchronous random access memory system comprising amemory, control logic for controlling the writing of data to and thereading of data from said memory; address storage registers for storingat least two addresses in said memory at which data is to be written orfrom which data is to be read in response to control signals; controlstorage registers for storing at least two control signals forcontrolling the writing of data to or the reading of data from saidmemory system; data storage registers for storing at least one set ofdata signals to be written into said memory, structure for receivingdata to be written into said memory and for also receiving data to beread out from said memory system, an address bus terminal coupled to afirst of said address storage registers for receiving the addresses ofdata to be written into the memory and to be read out of the memorysystem; and a control terminal coupled to a first of said data storageregisters for receiving control signals indicating whether data is to bewritten into the memory or read out of the memory system, wherein: in aread operation, said random access memory system is capable of providingdata at said structure for receiving data, said data corresponding to anaddress in said random access memory; in a write operation, said randomaccess memory system is capable of storing in said memory system writedata received at said structure for receiving data, said write datacorresponding to an address in said random access memory, and in a readoperation immediately following said write operation, said random accessmemory system is capable of outputting said write data at said structurefor receiving data, before said write data is written into said memory.2. The memory system of claim 1 wherein said structure for receivingdata comprises: an input bus for receiving data to be written into saidmemory, and an output bus for receiving data to be read out from saidmemory system.
 3. The memory system of claim 1 wherein said structurefor receiving data comprises: a data input/output bus terminal forreceiving data to be written into said memory and for also receivingdata to be read out from said memory system.
 4. The memory system ofclaim 1 wherein: in a write operation immediately following a readoperation, said random access memory system is capable of storing insaid memory write data received in said memory system prior to said readoperation, said write data being stored at an address in said memorysystem corresponding to an address stored in said address storageregisters.
 5. The memory system of claim 1 wherein said memory includes:an address port, a data-in port, a data-out port, and a control port. 6.The memory system recited in claim 5 wherein said memory system iscapable of placing into said data storage registers the write data to bewritten into said memory in conformance with said write operation and,in said read operation immediately following said write operation, iscapable of reading out from said memory system the read data associatedwith an address defined by said read operation, said read data comingfrom said memory if said address does not equal the address of the writedata stored in said data storage registers and said read data comingfrom said data storage registers if said address equals the address ofthe write data stored in said data storage registers.
 7. A synchronousrandom access memory system comprising a memory, at least one busterminal for receiving data to be written into said memory and for alsoreceiving data to be read out from said memory system, an address busterminal for receiving the addresses of data to be written into thememory and to be read out of the memory system; and a control terminalfor receiving control signals indicating whether data is to be writteninto the memory or read out of the memory system, wherein: in a readoperation, said random access memory system is capable of providing dataat said at least one bus terminal, said data corresponding to an addressin said random access memory; in a write operation, said random accessmemory system is capable of storing in said memory system write datareceived at said at least one bus terminal, said write datacorresponding to an address in said random access memory, and in a readoperation immediately following said write operation, said random accessmemory system is capable of outputting said write data at said at leastone bus terminal before said write data is written into said memory. 8.The memory system of claim 7 wherein: in a write operation immediatelyfollowing a read operation, said random access memory system is capableof storing in said memory write data previously stored in said memorysystem, said write data previously stored in said memory systemcorresponding to an address previously received on said address busterminal and stored in said memory system.
 9. The memory system of claim8 wherein: in a read operation immediately following a read operation,said random access memory system is capable of outputting at said atleast one bus terminal, data stored either in said memory or in saidrandom access memory system outside said memory.
 10. The memory systemof claim 9 wherein: in a write operation immediately following a writeoperation, said random access memory system is capable of storing insaid memory write data previously stored in said memory system.
 11. Thememory system of claim 10 wherein said memory includes: an address port,a data-in port, a data-out port, and a control port.
 12. The memorysystem recited in claim 11 further comprising: an input circuit coupledto said address bus terminal, said at least one bus terminal, saidcontrol terminal, said address port, said data-in port, said data-outport, and said control port wherein, during a write operation, saidinput circuit is capable of storing an address received from saidaddress bus terminal, a control signal received from said controlterminal, and write data corresponding to said address from said datainput/output bus terminal.
 13. The memory system recited in claim 12wherein said input circuit is capable of storing said write data in saidmemory during a write operation following the write operation duringwhich said address, said control signal and said write data were storedin said input circuit, and wherein said input circuit is not capable ofstoring said write data in said memory during a read operationimmediately following the write operation during which said address,said control signal and said write data were stored in said inputcircuit.
 14. The memory system recited in claim 13 further comprising: alogic circuit coupled to said input circuit and said memory, whereinsaid logic circuit is capable of causing said random access memorysystem to output said write data stored in said input circuit when,during a read operation, the address of said read operation matches saidaddress stored in said input circuit.
 15. The memory system recited inclaim 14 wherein said input circuit comprises: a first address registerhaving an input port and an output port, said input port being coupledto said address bus terminal; a second address register having an inputport coupled to said output port of said first address register and anoutput port coupled to said logic circuit; a control register having aninput terminal coupled to said control terminal and an output terminalcoupled to said logic circuit; and a data register having an input portcoupled to said at least one bus terminal and an output port coupled tosaid data-in port of said memory.
 16. The memory system recited in claim15 wherein said logic circuit comprises: a first multiplexer having: afirst input port coupled to said output port of said first addressregister; a second input port coupled to said output port of said secondaddress register; and an output port coupled to said address port ofsaid memory; a write enable circuit having an input terminal coupled tosaid output terminal of said control register and having an outputterminal coupled to the control port of said memory; a secondmultiplexer having a first input port coupled to said data-out port ofsaid memory, a second input port coupled to said output port of saiddata register, and an output port coupled to said at least one busterminal; and a comparator having a first input port coupled to saidoutput port of said first address register, a second input port coupledto said output port of said second address register, and an output portcoupled to the select input port of said second multiplexer.
 17. Amethod for accessing a synchronous random access memory, said methodcomprising: in a read operation, receiving a memory address in an nthclock cycle and outputting in an (n+1)th clock cycle data stored in saidsynchronous random access memory corresponding to said memory addressreceived in said nth clock cycle; and in a write operation, receiving ina kth clock cycle a memory address to which data is to be written, andreceiving in a (k+1)th clock cycle data to be stored in said synchronousrandom access memory at said memory address received in said kth clockcycle, wherein said nth clock cycle can be a clock cycle immediatelyfollowing said kth clock cycle with no clock cycles intervening betweensaid nth clock cycle and said kth clock cycle.
 18. The method of claim17 further comprising: storing data received in an rth write operationin an input circuit of said synchronous random access memory; andstoring during a (r+1)th write operation in a memory of said synchronousrandom access memory said data stored in said input circuit during saidrth write operation.
 19. The method of claim 18 further comprising:comparing an address received in a jth read operation to an addresscorresponding to data stored in said input circuit; and outputting datafrom said memory corresponding to said address received in said jth readoperation when said address received in said jth read operation does notmatch said address corresponding to data stored in said input circuitand outputting said data stored in said input circuit when said addressreceived in said jth read operation matches said address correspondingto data stored in said input circuit.
 20. A method for accessing asynchronous random access memory, said method comprising: in a readoperation, receiving a memory address in an nth clock cycle andoutputting in an (n+d)th clock cycle data stored in said synchronousrandom access memory corresponding to said memory address received insaid nth clock cycle; and in a write operation, receiving in a kth clockcycle a memory address to which data is to be written, and receiving ina (k+d)th clock cycle data to be stored in said synchronous randomaccess memory at said memory address received in said kth clock cycle,wherein said nth clock cycle can be a clock cycle immediately followingsaid kth clock cycle with no clock cycles intervening between said nthclock cycle and said kth clock cycle, wherein d equals a selectedinteger.
 21. The method of claim 20 wherein d equals
 1. 22. The methodof claim 20 wherein d equals
 2. 23. The method of claim 20 wherein dequals at least
 3. 24. A synchronous random access memory comprising: ina read operation, means for receiving a memory address in an nth clockcycle and outputting in an (n+d)th clock cycle data stored in saidsynchronous random access memory corresponding to said memory addressreceived in said nth clock cycle; and in a write operation, means forreceiving a memory address in a kth clock cycle and for receiving in a(k+d)th clock cycle data to be stored in said synchronous random accessmemory data at said memory address received in said kth clock cycle,wherein d equals any one of 1, 2, 3, 4, . . . N, where N is a selectedinteger.
 25. The memory of claim 24 wherein said nth clock cycle can bea clock cycle sequentially following said kth clock cycle with no clockcycles intervening between said nth clock cycle and said kth clockcycle.
 26. The memory of claim 24 wherein said kth clock cycle can be aclock cycle sequentially preceding said nth clock cycle with no clockcycles intervening between said nth clock cycle and said kth clockcycle.
 27. A memory system comprising: a memory array having: an addressport for receiving the addresses of data to be written into or read fromthe memory array; a control port for receiving write and read signals tocause data to be written into and read from the memory array; a data-inport for receiving data being written into the memory array; and adata-out port for outputting data being read out of the memory array; alogic circuit; a first address register for receiving an addresscorresponding to a write or read signal, said address register having anoutput bus connected by said logic circuit to said address port; a firstcontrol register for receiving a write signal or a read signal, saidfirst control register having an output terminal connected by said logiccircuit to said control port; at least one data bus for receiving datato be written into or read out of the memory system, said at least onedata bus being connected by said logic circuit to said data-out port;and a first data register having an input bus connected to said at leastone data bus and an output bus connectable by said logic circuit to saiddata-in port.
 28. The memory system as in claim 27 wherein said logiccircuit includes: a second address register for receiving an addressfrom said first address register, said second address register having aninput bus connected to the output bus of said first address register andan output bus; and a first comparator for comparing a first address insaid first address register to a second address in said second addressregister, and for producing a first signal if the first address equalsthe second address and for producing a second signal if the firstaddress does not equal the second address.
 29. The memory system as inclaim 28 wherein said logic circuit includes: a first multiplexercircuit for passing data stored in said first data register to the atleast one data bus in response to a read signal in said first controlregister when the first address equals the second address, and forpassing data stored in said memory array at the first address to the atleast one data bus when the first address does not equal the secondaddress.
 30. The memory system as in claim 29 wherein said logic circuitincludes: a second multiplexer circuit for passing the first address tosaid address port when the first control register contains a read signaland for passing the second address to said address port when the firstcontrol register contains a write signal.
 31. The memory system as inclaim 30 wherein said logic circuit includes: an output buffer betweensaid second multiplexer and the at least one data bus.
 32. The memorysystem of claim 31 wherein said output buffer is capable of assuming ahigh impedance or a low impedance.
 33. The memory system as in claim 30wherein said output buffer is a tristate buffer.
 34. The memory systemas in claim 28 wherein said logic circuit includes: a third addressregister having an input bus and an output bus; and a third multiplexercircuit for passing the address on the output bus of said second addressregister to the input bus of said third address register oralternatively for passing the address on the output bus from the firstaddress register to the input bus of the third address register.
 35. Amemory system as in claim 34 wherein said logic circuit includes: asecond data register, having an input bus connected to the output bus ofsaid first data register, and an output bus connectable to the datain-port of the memory array.
 36. The memory system as in claim 35including: an output register having an input bus and an output bus,said input bus being connectable to the data out-port of said memoryarray, to the output bus of said first data register, to the output busof said second data register and to said at least one data bus of saidmemory system.
 37. The memory system as in claim 36 including: a fourthmultiplexer for passing data being read out from the data out-port or onsaid output bus from said first data register; a fifth multiplexer forpassing data passed by said fourth multiplexer or from the output bus ofsaid output register; and an output buffer for passing the data outputfrom said fifth multiplexer to the at least one data bus of the memorysystem.
 38. The memory system as in claim 37 including: a secondcomparator for comparing a first address in said first address registerto a third address in said third address register and for producing athird signal if the first address equals the third address and forproducing a fourth signal if the first address does not equal the thirdaddress.
 39. A structure which comprises: a memory circuit; an inputcircuit coupled to receive a memory address, a read/write control signaland write data to be written into the memory, said input circuitincluding one or more storage registers for storing the write data to bewritten into the memory prior to writing the write data into the memory;and a logic circuit for causing the stored write data to be written fromthe input circuit into the memory during the pth write operationfollowing the write operation during which said write data was placed insaid storage registers, while causing the write data to be held in thestorage registers during any intervening read and write operations,where p is a selected integer given by 1≦p≦P.
 40. A structure as inclaim 39 including: means for holding the write data in said storageregisters during one or more read operations immediately following thewrite operation during which said write data was placed in said storageregisters.
 41. A structure as in claim 40 including: means for readingout data from said memory and from one of said storage registers duringone or more read operations directly following said write operation,said data being read from one of said storage registers when the addressof said data to be read from the memory corresponds to the address ofthe data stored in one of said storage registers and said data beingread from the memory when the address of said data being read does notcorrespond to the address of the data stored in one of said storageregisters.
 42. The method of writing data into memory and reading datafrom a memory system which includes said memory which comprises: placingwrite data to be stored in said memory and the address at which saidwrite data is to be stored into storage registers external to saidmemory, storing said write data in said storage registers during theexecution of one or more read cycles, reading said write data stored insaid storage registers out of the memory system should the address ofthe data to be read from the memory system correspond to the address ofthe write data stored in said storage registers and reading the data outof said memory should the address of the data to be read from the memorysystem not correspond to the address of the write data stored in saidstorage registers; and writing the write data stored in said storageregisters into said memory on a subsequent write cycle.
 43. The methodof claim 42 wherein the write data to be written into said memoryappears on a Data I/O bus to said memory system p cycles after theaddress and write control signal are placed on the address input bus andcontrol input bus, respectively, to said memory system, where p is aselected integer given by 1≦p≦P.
 44. The method as in claim 43 whereinsaid write data to be written into said memory system appears on a DataI/O bus to said memory system two clock cycles after the address and thewrite control signal appear on the address bus and the control bus tosaid memory system.
 45. The method as in claim 43 wherein said writedata to be written into said memory system appears on a Data I/O bus tosaid memory system one clock cycle after the address and the writecontrol signal appear on the address bus and the control bus to saidmemory system.
 46. The method of claim 43 wherein said write data to bewritten into said memory is stored in a storage register outside saidmemory when one or more read commands are received in sequenceimmediately following said write operation and said write data iswritten into said memory on the next write operation following the writeoperation during which the write data was placed on the Data I/O bus ofthe memory system.
 47. The method of claim 44 wherein said memory systemis capable of holding up to two sets of write data in storage registersoutside said memory for the duration of a sequence of one or more readoperations following said two write operations, said system thenallowing the oldest write data to be written into said memory uponreceipt of the next following write control signal.
 48. The method ofclaim 46 wherein the operation of said system is such that the Data I/Obus of the system, for each cycle of-operation, carries either writedata to be written into the memory or data read out from the memory,thereby to increase the bandwidth of the memory system.
 49. The methodof claim 47 wherein the operation of said system is such that the DataI/O bus of the system for each cycle of operation, carries either writedata to be written into the memory or data read out from the memory,thereby to increase the bandwidth of the memory system.